1. Field of the Invention
This invention relates generally to semiconductor manufacturing, and, more particularly, to a method and apparatus for reducing non-uniformity across a processed semiconductor wafer using a dynamic process adjustment in a tool.
2. Description of the Related Art
The technology explosion in the manufacturing industry has resulted in many new and innovative manufacturing processes. Today""s manufacturing processes, particularly semiconductor manufacturing processes, call for a large number of important steps. These process steps are usually vital, and therefore, require a number of inputs that are generally fine-tuned to maintain proper manufacturing control.
The manufacture of semiconductor devices requires a number of discrete process steps to create a packaged semiconductor device from raw semiconductor material. The various processes, from the initial growth of the semiconductor material, the slicing of the semiconductor crystal into individual wafers, the fabrication stages (etching, doping, ion implanting, or the like), to the packaging and final testing of the completed device, are so different from one another and specialized that the processes may be performed in different manufacturing locations that contain different control schemes.
Generally, a set of processing steps is performed across a group of semiconductor wafers, sometimes referred to as a lot. For example, a process layer composed of a variety of materials may be formed across a semiconductor wafer. Thereafter, a patterned layer of photoresist may be formed across the process layer using known photolithography techniques. Typically, an etch process is then performed across the process layer using the patterned layer of photoresist as a mask. This etching process results in the formation of various features or objects in the process layer. Such features may be used for a gate electrode structure for transistors. Many times, trench isolation structures are also formed across the substrate of the semiconductor wafer to isolate electrical areas across a semiconductor wafer. One example of an isolation structure that can be used is a shallow trench isolation (STI) structure. Typically, forming trenches across the semiconductor wafer and filling such trenches with an insulating material, such as silicon dioxide, form STI structures across the semiconductor wafers.
The manufacturing tools within a semiconductor manufacturing facility typically communicate with a manufacturing framework or a network of processing modules. Each manufacturing tool is generally connected to an equipment interface. The equipment interface is connected to a machine interface to which a manufacturing network is connected, thereby facilitating communications between the manufacturing tool and the manufacturing framework. The machine interface can generally be part of an advanced process control (APC) system. The APC system initiates a control script, which can be a software program that automatically retrieves the data needed to execute a manufacturing process.
FIG. 1 illustrates a typical semiconductor wafer 105. The semiconductor wafer 105 typically includes a plurality of individual semiconductor die 103 arranged in a grid 150. Using known photolithography processes and equipment, a patterned layer of photoresist may be formed across one or more process layers that are to be patterned. As part of the photolithography process, an exposure process is typically performed by a stepper on approximately one to four die 103 locations at a time, depending on the specific photomask employed. The patterned photoresist layer can be used as a mask during etching processes, wet or dry, performed across the underlying layer or layers of material, e.g., a layer of polysilicon, metal or insulating material, to transfer the desired pattern to the underlying layer. The patterned layer of photoresist is comprised of a plurality of features, e.g., line-type features or opening-type features that are to be replicated in an underlying process layer.
Turning now to FIG. 2, a flow chart illustration of a prior art process flow is illustrated. A manufacturing system processes a lot/batch of semiconductor wafers 105 (block 210). The manufacturing system then generally acquires metrology data relating to the processed semiconductor wafers 105 (block 220). The manufacturing system may also acquire sensor data, such as pressure sensor data, temperature sensor data, humidity sensor data, gas flow rate sensor data, and the like. Generally, the manufacturing system then analyzes the metrology data and/or the sensor data to determine whether there are appreciable errors across the processed semiconductor wafers 105 (block 230).
The manufacturing system may then perform feedback and/or feed-forward corrections on processes performed across the semiconductor wafers 105 based upon the analysis of the metrology/sensor data (block 240). One of the problems associated with the current processing system is the production of non-uniformly processed semiconductor wafers, which may be due to processes performed across the semiconductor wafers 105 (hereinafter referred to as xe2x80x9cprocess non-uniformityxe2x80x9d). In other words, results from processing may not be uniform across the entire semiconductor wafer 105, which is a condition that may not be detected by simply analyzing the metrology/sensor data as described above. For example, a chemical mechanical polishing (CMP) tool may polish the center of a semiconductor wafer 105 at a different speed than the outer portion of a semiconductor wafer 105. This may result in non-uniform polishing across the processed semiconductor wafer 105. In other cases, a gradient effect may occur across a semiconductor wafer 105, wherein one portion of the semiconductor wafer 105 may be processed differently from another portion. For example, during an etch process, the left half of a semiconductor wafer 105 may be etched at a faster rate than the right half of the semiconductor wafer 105, resulting in non-uniform etching across the semiconductor wafer 105.
Non-uniformity across processed semiconductor wafers 105 may result in improper correction of errors detected across the processed semiconductor wafer 105. Furthermore, devices produced from the processed semiconductor wafer 105 may be of varying qualities, wherein devices produced from the inner portion of the semiconductor wafers 105 may be of inferior quality as compared to devices produced from the outer sections of a processed semiconductor wafer 105, or vice versa. Additionally, performance of devices manufactured from one portion of the non-uniform semiconductor wafers 105 may significantly vary from the performance of devices manufactured from another portion of the semiconductor wafers 105. Furthermore, prediction of yield and/or other manufacturing planning may be adversely affected due to non-uniform areas that may exist across the processed semiconductor wafers 105.
The present invention is directed to overcoming, or at least reducing, the effects of, one or more of the problems set forth above.
In one aspect of the present invention, a method is provided for reducing process non-uniformity across a processed semiconductor wafers. A first semiconductor wafer is processed. A process non-uniformity associated with the first processed semiconductor wafer is identified. A feedback correction in response to the process non-uniformity during processing of a second semiconductor wafer is performed and/or a feed-forward compensation is performed in response to the process non-uniformity during a subsequent process performed across the first semiconductor wafer is performed.
In another aspect of the present invention, a system is provided for reducing process non-uniformity across a processed semiconductor wafers. The system of the present invention comprises: a process controller adapted to control processing of a first processed semiconductor wafer; a uniformity detection unit operatively coupled to the process controller, the uniformity detection unit being adapted to determine an area of non-uniformity across the first processed semiconductor wafer; and a feedback non-uniformity correction unit operatively coupled to the uniformity detection unit and to the process controller, the feedback non-uniformity correction unit being adapted to modify a process variable relating to the area of process non-uniformity during processing of a second semiconductor wafer.
In yet another aspect of the present invention, a computer readable program storage device encoded with instructions is provided for reducing process non-uniformity across semiconductor wafers. The computer readable program storage device encoded with instructions when executed by a computer: processes a first semiconductor wafer; identifies a process non-uniformity associated with the first processed semiconductor wafer; and performs a feedback correction in response to the process non-uniformity during processing of a second semiconductor wafer, and/or a feed-forward compensation in response to the process non-uniformity during a subsequent process performed across the first processed semiconductor wafer.